Microelectronics | ISA I/O INTERFACE
Synopsis
After successfully building the 16-BIT ATX ISA Backplane and the 32-bit 80386DX ISA Single Board Microcomputer, I decided to replace all other factory built ISA cards from my homemade computer with DIY ones. Sure thing, an ISA I/O interface card would make for a nice project while providing some connectivity options to the system.
Here are the hardware specifications.
- One Floppy Disk Drive Controller with two channels (Floppy A, Floppy B)
- Two IDE Interfaces with two channels each (primary master-slave, secondary master-slave)
- Two Serial Port Controllers (COM1 / COM3, COM2 / COM4)
- One Parallel Port Controller (LPT1)
- Two Option ROM for the ROM BIOS IDE software configuration program
- Minimal Glue Logic
- Individual hardware configuration switches and jumpers for all functions
- 16-bit ISA-class printed circuit board construction
For easier reproduction of this design, I tried to source chips that are still being produced. However, some parts prove difficult to find -- think parallel port controller chip. But everything is possible in the Internet era. With a bit of luck, you can find any computer chip on-line and have it delivered to your door in less than a month.
As always, you can find the bill of materials (BOM) below after the schematic diagrams and the computer simulations of the final printed circuit board layouts. The schematic is nothing but a collection of computer peripherals, most of it being based on application notes and original datasheets. The IDE host adapter interface is particularly interesting since it contains a programmable logical device. Other than that, everything is straightforward. It might appear that the schematic is a bit overengineered. If you compare it with similar schematics of cost-cutting ISA PCBs of the time, then yes, it is overengineered. But if you take a look at, for instance, IBM period correct implementations, you will find that my schematic is less overengineered than theirs. Since this is a hobby project, I don't have any cost-related issues. I don't plan to do mass production, nor do I hurry anywhere. Thus, I can wait enough time so that I can raise the required funds for this project. So that was basically what I did. I ordered parts in batches as soon as I got the required funds.
The main motivation for building this ISA card is the implementation of a dual IDE interface. This was mostly unheard of in the early 386 days. For it to fully function properly, it will require a separate ROM BIOS program. The system ROM BIOS of my 386 machine knows how to address only one interface. So there is another challenge here. Furthermore, I have never had any chance of working with PALs, so it was a good idea to start somewhere. I'm eager to write the PAL equations and then produce the controller firmware. While it's true I programmed CPLDs in the past, PALs are something new to me. Another interesting thing that always bugged me is hardware decoding of peripheral addresses. I used these hardware addresses in my software in the '90s but I never ever thought about how the decoding is done at the implementation level. So, back to the drawing board. Literally. Well, mostly paper and pencil. Drawing massive logic charts for the decoders was a challenge of its own. But I had my share of fun. I wouldn't do anything if I didn't have fun doing it.
All in one, the I/O interface card is something that I would've loved to have back in the early 1990s. Nowadays, it is quasi-useless. But still a nice project for retrocomputing enthusiasts.
Disclaimer: I reserve the right to change the schematic diagram, the PCB layout, or the implementation without further notice. This is an entirely hobby do-it-yourself design and I am not responsible for any damage made by any possible mistake in any version or revision of the schematic diagrams or PCB layouts. Since it is an advanced microelectronics project, it requires very good assembly and debugging skills. In addition, I cannot offer any further technical support other than the contents of this article.
This project is in its final stage.
Current iteration of ASSY. 2486-IOIF-301 is VER. 1.4 REV. D
* * *
Laudatur ab his, culpatur ab illis. This project is provided as-is and is not for commercial purposes. It reflects my experimental work in microcomputer system design and should be treated as such. I release the schematic diagram and circuit board layouts to the public for educational purposes. I did all this at my own expense and in my free time. If you like my work, please consider making a donation. It helps me continue these kind of projects.
Schematic Diagram (VER. 1.4 REV. D)
Fig. 1: Electrical Schematic Diagram
Printed Circuit Boards
Fig. 2: Top Silkscreen
Fig. 3: Bottom Silkscreen
Fig. 4: Top Layer Printed Circuit Board
Fig. 5: Inner Bottom Layer Printed Circuit Board
Fig. 6: Inner Top Layer Printed Circuit Board
Fig. 7: Bottom Layer Printed Circuit Board
Fig. 8: Top Layer Printed Circuit Board - Simulation
Fig. 9: Bottom Layer Printed Circuit Board - Simulation
If you want to see or hide older schematic diagrams please use the following function: Show Older Schematic Diagrams
Gerber Files
Here are the Gerber files compressed in a .ZIP archive.
Please note that the file naming convention that I used is what OSHPark normally expects.
You can also order the printed circuit board directly from OSHPark by following the link in the bill of materials below.
Compressed Gerber Files: isa-io-interface.zip
Bill of Materials (BOM)
The following list contains the parts that are required to assemble this ISA I/O interface card.
| ISA I/O INTERFACE | ||||
|---|---|---|---|---|
| Identifier | Value | Qty | Notes | Mouser Number |
| Printed Circuit Board | ASSY. 2486-IOIF-301 | 1 | VER. 1.4 REV. D | Order from OSHPark |
| IC1 | PC8477BV | 1 | Floppy Disk Controller | Order from 3rd Parties |
| IC2 | 74LS30 | 1 | Single 8-input NAND Gate | 595-SN74LS30N |
| IC3 | 74ALS04 | 1 | Hex Inverter | 595-SN74ALS04BN |
| IC4 | 74LS07 | 1 | Hex Buffer (OC) | 595-SN74LS07N |
| IC5-IC8 | 74ALS245 | 4 | Octal Bus Transceiver | 595-SN74ALS245AN |
| IC9 | 74ALS244 | 1 | Octal 3-state Buffer | 595-SN74ALS244CN |
| IC10 | ATF16V8B | 1 | EEPLD | 556-AF16V8B15PU |
| IC11, IC16 | 74ALS138 | 2 | 3:8 Line Decoder | 595-SN74ALS138AN |
| IC12 | 74ALS10 | 1 | Triple 3-input NAND Gate | 595-SN74ALS10AN |
| IC13, IC14 | 74F125 | 2 | Quad 3-state Buffer | 595-SN74F125N |
| IC15 | HT6535 | 1 | Parallel Port Controller | Order from 3rd Parties |
| IC17, IC18 | TL16C550 | 2 | Serial Port Controller | 595-TL16C550CFN |
| IC19, IC20 | SN75C185 | 2 | Serial Port Transceiver | 595-SN75C185N |
| IC21, IC23 | 74LS688 | 2 | Magnitude Comparer | 595-SN74LS688N |
| IC22, IC24 | 28C64 | 2 | 64 Kbit ROM | 556-AT28C64B15PU |
| D1-D9 | 1N4148 | 9 | Small Signal Diode | 78-1N4148 |
| C1-C36, C42, C44 | 100 nF / 50 V | 38 | MLCC | 80-C322C104M5R-TR |
| C37-C41, C43, C45 | 10 uF / 25 V | 7 | Tantalum Capacitor | 80-T350E106M025AT |
| C46-C49 | 33 pF / 50 V | 4 | MLCC | 80-C315C330J5G |
| C50-C66 | 180 pF / 50 V | 17 | MLCC | 80-C315C181K5R |
| C67-C82 | 100 pF / 50 V | 16 | MLCC | 80-C315C101K5R |
| C83 | 4.7 nF / 50 V (optional) | 1 | MLCC | 80-C315C472K5R |
| R1, R7 | 1 MΩ | 2 | Carbon Resistor | 291-1M-RC |
| R2, R3 | 1 kΩ | 2 | Carbon Resistor | 291-1K-RC |
| R4-R6, R8, R9 | 10 kΩ | 5 | Carbon Resistor | 291-10K-RC |
| R10 | 4.7 kΩ | 1 | Carbon Resistor | 291-4.7K-RC |
| RN1 | 5 x 150 Ω | 1 | Bussed Resistor Network | 652-4606X-1LF-150 |
| RN2-RN5 | 8 x 1 kΩ | 4 | Bussed Resistor Network | 652-4609X-1LF-1K |
| RN6 | 5 x 4.7 kΩ | 1 | Bussed Resistor Network | 652-4606X-1LF-4.7K |
| RN7, RN8 | 8 x 10 kΩ | 2 | Bussed Resistor Network | 652-4609X-1LF-10K |
| RA1 | 5 x 470 Ω | 1 | Resistor Array | 652-4610X-2LF-470 |
| RA2 | 4 x 10 kΩ | 1 | Resistor Array | 652-4608X-2LF-10K |
| RA3 | 3 x 470 Ω | 1 | Resistor Array | 652-4606X-2LF-470 |
| L1-L33 | BL03RN2 | 33 | Ferrite Bead | 81-BL03RN2R1P1A |
| X1, X2 | 24 MHz | 2 | Quartz Crystal | 695-HC49US-24-U |
| X3 | 1.8432 MHz | 1 | Quartz Oscillator | 520-TCF184-X |
| F1-F3 | 1.1 A | 3 | Resettable Fuse | 576-16R110BU |
| SW1 | 6-position | 1 | DIP Switch | 774-2066 |
| SW2 | 4-position | 1 | DIP Switch | 774-2064 |
| SW3 | 7-position | 1 | DIP Switch | 774-2067 |
| SW4 | 7-position | 1 | DIP Switch | 774-2067 |
| LED1 | 5 mm Orange LED | 1 | FDA Activity Indicator | 755-SLR-56DC3F |
| LED2 | 5 mm Orange LED | 1 | FDB Activity Indicator | 755-SLR-56DC3F |
| LED3 | 5 mm Red LED | 1 | IDE1 Activity Indicator | 755-SLR-56VC3F |
| LED4 | 5 mm Red LED | 1 | IDE2 Activity Indicator | 755-SLR-56VC3F |
| LED5 | 5 mm Yellow LED | 1 | ROM Activity Indicator | 755-SLR-56YC3F |
| IC Socket | 68-pin PLCC | 2 | IC1, IC15 | 575-682444 |
| IC Socket | 14-pin | 6 | IC2-IC4, IC12-IC14 | 575-193314 |
| IC Socket | 20-pin | 10 | IC5-IC10, IC19-IC21, IC23 | 575-193320 |
| IC Socket | 16-pin | 2 | IC11, IC16 | 575-110433161 |
| IC Socket | 44-pin PLCC | 2 | IC17, IC18 | 575-944424 |
| IC Socket | 28-pin | 2 | IC22, IC24 | 575-11043628 |
| JP2, JP5-JP7, JP10-JP12 | 2-pin Header | 7 | Jumper | 649-68001-202HLF |
| JP1, JP3, JP4, JP8, JP9, JP13-JP19 | 3-pin Header | 12 | Jumper | 649-68001-203HLF |
| J1-J3 | 2-pin Header | 3 | Header | 649-68001-202HLF |
| J4 | 34-pin Connector | 1 | Header | 617-09185345324 |
| J5, J6 | 40-pin Connector | 2 | Header | 617-09185405324 |
| J7 | 10-pin Connector | 1 | Header | 617-09185105324 |
| J8 | 25-pin Connector | 1 | Female D-Sub | 617-09683537612 |
| J9 | 9-pin Connector | 1 | Male D-Sub | 617-09681637813 |
| Screw | Screwlock 4-40 UNC | 4 | For J8, J9 | 617-09670019941 |
Alternatively you can use the following link to the Mouser project that I created for this ISA card. It should make ordering of parts and removing typing faults pretty easy.
Mouser Project: ISA I/O INTERFACE
Lately I have observed that Mouser discontinued some of the parts in the list above. If you decide to build this project, then you need to find alternatives. It is out of my scope to maintain the correctness of the parts list above.
Assembly Instructions and Notes
Here is a list of things you need to pay attention to should you decide to build such ISA I/O interface card.
- Inspect the printed circuit board once you receive it. Normally OSHPark produces very good quality boards but one never knows. There must be absolutely no short circuits on the printed tracks. If the PCB is faulty then it can damage other ISA cards that you might install in the system.
- Carefully observe polarity of the tantalum electrolytic capacitors on the silkscreen. I made sure there is no error on the printout. Tantalum capacitors will violently explode and burst in fire if mounted in reverse, possibly injuring you.
- Take your time to solder all the components on the board. There are a lot of solder points and if you don't have patience in general, then this project might not be for you.
- Use a temperature-controlled soldering station and quality solder. Take care not to leave solder bridges as any short circuit will most likely lead to failures.
- In order to ease-up the PCB assembly, I would suggest mounting parts in the following order: diodes, resistors, quartz crystals, quartz oscillator, IC sockets, resistor networks, MLCC capacitors, tantalum capacitors, switches, LEDs, jumpers, pin headers, ferrite beads, connectors.
- At the end, clean any flux residues with isopropyl alcohol.
- In case you decide to experiment with option ROMs then make sure you configure the ROM address range accordingly. It must not interfere with other ROMs installed in the system.
Principle of Operation
This ISA I/O interface card is PC AT compatible and was designed with a 16-bit ISA slot in mind. It is basically a cumulus of different PC interface peripherals that are crowded on the same PCB assembly. While the PCB looks unified and it gives the impression that the parts are interconnected, in reality they are all individual sub-schematics of the main electrical schematic diagram. The modules share the power rails and the ISA signaling lines. In fact, each interface could be built separately on its own ISA card. But that would imply a big waste of space and resources.
I initially wanted to draw a block diagram that illustrates the principle of operation. But then again, the schematic is well drawn and clearly expresses the individual functional blocks.
One thing that was corrected in VER. 1.4 REV. D is the fact that now the SPSYNC:CSEL signal of each individual IDE interface can be switched either to the GND or the ALE signal. When I drew the original schematic diagram, I implemented the IDE interfaces as described by the earliest IDE standards. Pin 28 was originally called Drive Address Latch Enable (DALE signal) and was designed to connect to the ALE signal of the ISA bus. It was used to indicate a valid address from the host system. But then, in 1994, the ANSI X3.221-1994 standard appeared. It described the AT Attachment Interface for Disk Drives (ATA-1) and pin 28 was re-purposed as SPSYNC:CSEL signal. While the SPSYNC signal is of no interest to me whatsoever, the CSEL signal actually is. Let's find out why.
After finishing the assembly of PCB VER. 1.4 REV. C, I tested it with a bunch of mechanical hard disk drives ranging from 40 Mb stepper motor models to 4.3 Gb voice coil models. They all worked perfectly in all sorts of master-slave combinations. Then I also tested four identical 512 Mb Compact Flash cards in all sorts of combinations. And they all worked. The issue was when I tried to test Transcend Industrial 2 Gb and 4 Gb Compact Flash cards. These refused detection by all means. They would register and work only in a certain combination: Transcend Industrial card as master and 512 Mb STI Flash card as slave. All other combinations failed for some reason.
So I started reading the ATA-1 papers and the ALE signal is not required anymore for modern mechanical drives or CF cards. That means pin 28 of the physical IDE interfaces should be tied to something else. The paper describes the connection of the CSEL signal as follows.
- if CSEL is tied to GND signal then the drive is configured as master
- if CSEL is not connected then the drive is configured as slave
I immediately modified the CF adapters that I was using so that they reflected this hard-wired connection of pin 28 to either the GND signal or left unconnected, and surprise: the Transcend Industrial cards came to life. Also, while reading the datasheet for the Transcend CF220I series of compact flash cards, I learned the card CSEL signal is internally pulled up to allow configuration of the device as either master or slave in true IDE mode. This fulfills the X3.221 standard requirements of pulling this line up with a 10 kΩ resistor. Thus, nothing to do at the PCB level in this case.
Also, another weird behavior of using the ALE signal along with four 512 Mb CF cards was that the Intel EtherExpress 16TP network card was not registering anymore. Apparently there was a conflict with something called mainboard resources. Well, mainboard is not the appropriate word because I was using an ISA Pentium MMX 233 MHz single board computer. Removing the ALE signal from the CF adapters solves this issue as well.
Interface Connectors Description
The following section describes all the interface connectors and their respective pinouts.
| INTERFACE CONNECTORS DESCRIPTION | |||
|---|---|---|---|
| Identifier | Value | Notes | Pinout |
| J1 | IDE | IDE Activity LED | 1 - LED Anode 2 - LED Cathode |
| J2 | IDE2 | IDE2 Activity LED | 1 - LED Anode 2 - LED Cathode |
| J3 | IDE1 | IDE1 Activity LED | 1 - LED Anode 2 - LED Cathode |
| J4 | FLOPPY INTERFACE | Floppy Disk Drive | 1 - VSS 2 - /DENSEL 3 - VSS 4 - NC 5 - VCC/VSS 6 - /DRATE 7 - VSS 8 - /INDEX 9 - VSS 10 - /MEA 11 - VSS 12 - /DSB 13 - VSS 14 - /DSA 15 - VSS 16 - /MEB 17 - VSS 18 - /DIR 19 - VSS 20 - /STEP 21 - VSS 22 - /WRDATA 23 - VSS 24 - /WE 25 - VSS 26 - /TRK00 27 - VSS 28 - /WP 29 - VSS 30 - /RDDATA 31 - VSS 32 - /HDSEL 33 - VSS 34 - /DSKCHG |
| J5 | PRIMARY IDE INTERFACE | Hard Disk Drive | 1 - /RESET 2 - VSS 3 - IDE1-D7 4 - IDE1-D8 5 - IDE1-D6 6 - IDE1-D9 7 - IDE1-D5 8 - IDE1-D10 9 - IDE1-D4 10 - IDE1-D11 11 - IDE1-D3 12 - IDE1-D12 13 - IDE1-D2 14 - IDE1-D13 15 - IDE1-D1 16 - IDE1-D14 17 - IDE1-D0 18 - IDE1-D15 19 - VSS 20 - NC/VCC 21 - NC 22 - VSS 23 - /IDE1-IOW 24 - VSS 25 - /IDE1-IOR 26 - VSS 27 - NC/IDE1-IORDY 28 - ALE/VSS 29 - NC 30 - VSS 31 - IRQ14 32 - /I/OCS16 33 - A1 34 - NC 35 - A0 36 - A2 37 - /CS1FX 38 - /CS3FX 39 - /IDE1-ACT 40 - VSS |
| J6 | SECONDARY IDE INTERFACE | Hard Disk Drive | 1 - /RESET 2 - VSS 3 - IDE2-D7 4 - IDE2-D8 5 - IDE2-D6 6 - IDE2-D9 7 - IDE2-D5 8 - IDE2-D10 9 - IDE2-D4 10 - IDE2-D11 11 - IDE2-D3 12 - IDE2-D12 13 - IDE2-D2 14 - IDE2-D13 15 - IDE2-D1 16 - IDE2-D14 17 - IDE2-D0 18 - IDE2-D15 19 - VSS 20 - NC/VCC 21 - NC 22 - VSS 23 - /IDE2-IOW 24 - VSS 25 - /IDE2-IOR 26 - VSS 27 - NC/IDE2-IORDY 28 - ALE/VSS 29 - NC 30 - VSS 31 - IRQ15 32 - /I/OCS16 33 - A1 34 - NC 35 - A0 36 - A2 37 - /CS17X 38 - /CS37X 39 - /IDE2-ACT 40 - VSS |
| J7 | SERIAL PORT 2 | COM2 / COM4 | 1 - DCD 2 - RX 3 - TX 4 - DTR 5 - VSS 6 - DSR 7 - RTS 8 - CTS 9 - RI 10 - NC |
| J8 | SERIAL PORT 1 | COM1 / COM3 | 1 - DCD 2 - RX 3 - TX 4 - DTR 5 - VSS 6 - DSR 7 - RTS 8 - CTS 9 - RI |
| J9 | PARALLEL PORT 1 | LPT1 | 1 - /STROBE 2 - PD0 3 - PD1 4 - PD2 5 - PD3 6 - PD4 7 - PD5 8 - PD6 9 - PD7 10 - ACK 11 - /BUSY 12 - PE 13 - /SELECT 14 - /LF 15 - ERROR 16 - INIT 17 - /SLTIN 18 - VSS 19 - VSS 20 - VSS 21 - VSS 22 - VSS 23 - VSS 24 - VSS 25 - VSS |
ISA Card Configuration
I have provided some basic card configuration options under the form of jumpers.
The star (*) symbol signifies the default option.
| ISA CARD CONFIGURATION | |||
|---|---|---|---|
| Identifier | Value | Notes | Configuration |
| JP1 | MODE | FDD Mode | 1-2: Enabled (*) 2-3: Disabled |
| JP2 | DRATE | FDD Data Rate | CL: Extended (2.88M) OP: Standard (*) |
| JP3 | POWER | PS/2 FDD Power | 1-2: Cable 2-3: External (*) |
| JP4 | MODE | IDE1 Mode | 1-2: Enabled (*) 2-3: Disabled |
| JP5 | IORDY | IDE1 I/O Ready | CL: Enabled OP: Disabled (*) |
| JP6 | CFPWR | IDE1 CF Power | CL: Enabled OP: Disabled (*) |
| JP7 | PU | IDE1 Pull-up Resistors | CL: Enabled (*) OP: Disabled |
| JP8 | CSEL | IDE1 SPSYNC:CSEL | 1-2: Enabled (*) 2-3: ISA-ALE |
| JP9 | MODE | IDE2 Mode | 1-2: Enabled (*) 2-3: Disabled |
| JP10 | IORDY | IDE2 I/O Ready | CL: Enabled OP: Disabled (*) |
| JP11 | CFPWR | IDE2 CF Power | CL: Enabled OP: Disabled (*) |
| JP12 | PU | IDE2 Pull-up Resistors | CL: Enabled (*) OP: Disabled |
| JP13 | CSEL | IDE2 SPSYNC:CSEL | 1-2: Enabled (*) 2-3: ISA-ALE |
| JP14, JP15 | MODE | LPT1 Mode | 2-3, 2-3: ISA (*) 1-2, 2-3: PS/2 2-3, 1-2: EPP 1-2, 1-2: ECP |
| JP16, JP17 | ADDRESS | LPT1 Address | 2-3, 2-3: 0x378h (*) 1-2, 2-3: 0x278h 2-3, 1-2: 0x3BCh 1-2, 1-2: Disabled |
| JP18 | ROM0SZ | ROM #0 SIZE | 1-2: 64 Kbit (*) 2-3: 256 Kbit |
| JP19 | ROM1SZ | ROM #1 SIZE | 1-2: 64 Kbit (*) 2-3: 256 Kbit |
Some other configuration options are provided under the form of switches.
Again, the star (*) symbol signifies the default option.
| ISA CARD CONFIGURATION | |||
|---|---|---|---|
| Identifier | Value | Notes | Configuration |
| SW1.1, SW1.2 | IRQ | LPT1 Interrupt Request | ON, OFF: IRQ5 OFF, ON: IRQ7 (*) |
| SW1.3, SW1.4 | DRQ | LPT1 DMA Request | ON, OFF: DRQ1 OFF, ON: DRQ3 (*) |
| SW1.5, SW1.6 | DACK | LPT1 DMA Acknowledge | ON, OFF: DACK1 OFF, ON: DACK3 (*) |
| SW2.1, SW2.3 | ADDRESS | Serial Port 2 Address | ON, OFF: 0x2E8h, COM4 OFF, ON: 0x2F8h, COM2 (*) |
| SW2.2, SW2.4 | ADDRESS | Serial Port 1 Address | ON, OFF: 0x3E8h, COM3 OFF, ON: 0x3F8h, COM1 (*) |
| SW3.1 | ROM #0 | Mode | ON: ENABLED OFF: DISABLED (*) |
| SW3.2 | ROM #0 | Write | ON: ENABLED OFF: DISABLED (*) |
| SW4.1 | ROM #1 | Mode | ON: ENABLED OFF: DISABLED (*) |
| SW4.2 | ROM #1 | Write | ON: ENABLED OFF: DISABLED (*) |
Option ROM Configuration
The two option ROMs can contain microcode that could act as a Basic Input/Output System (BIOS) for the IDE interface 1 and 2 configuration. At the moment, I have not written such a program but I am planning to do so. Anyway, in order to reach this microcode, a valid start address needs to be supplied to each individual ROM decoder circuit. This is done by configuring the SW3 and SW4 switch arrays. From the table above, we already know that in order to enable option ROM #0, SW3.1 needs to be set to ON. The 74LS688 magnitude comparator will be active once the CPU has control of the address and data bus. In other words, /G signal will be active when AEN is not asserted (low). Then SW3.2 needs to be set to OFF. That means ROM #0 /WE signal is not active. Which is normal since we don't want to provide writing capabilities to a non-writable memory. However, this switch is useful for programming an empty ROM directly in-place. Similarly, switches SW4.1 and SW4.2 control the availability of ROM #1 to the system.
A combination of SW3.3, SW3.4, SW3.5, SW3.6, and SW3.7 will dictate the start address for option ROM #0. Some combinations will generate conflicts with System BIOS or other option ROMs that might be present in the system. So double check their actual address range before configuring the on-board option ROM start address.
In addition, a combination of SW4.3, SW4.4, SW4.5, SW4.6, and SW4.7 will dictate the start address for option ROM #1. Needless to say that the address of ROM #0 must be totally different than the address of ROM #1. And neither of them should conflict with other ROMs in the system.
| OPTION ROM CONFIGURATION | ||||||||
|---|---|---|---|---|---|---|---|---|
| Combination | SW3/4.3 | SW3/4.4 | SW3/4.5 | SW3/4.6 | SW3/4.7 | Start Address | End Address | Conflict |
| 1 | ON | ON | ON | ON | ON | 0xC0000 | 0xC1FFF | EGA/VGA BIOS |
| 2 | ON | ON | ON | ON | ON | 0xC2000 | 0xC3FFF | EGA/VGA BIOS |
| 3 | ON | ON | ON | ON | ON | 0xC4000 | 0xC5FFF | EGA/VGA BIOS |
| 4 | ON | ON | ON | ON | ON | 0xC6000 | 0xC7FFF | EGA/VGA BIOS |
| 5 | ON | ON | ON | ON | ON | 0xC8000 | 0xC9FFF | |
| 6 | ON | ON | ON | ON | ON | 0xCA000 | 0xCBFFF | |
| 7 | ON | ON | ON | ON | ON | 0xCC000 | 0xCDFFF | |
| 8 | ON | ON | ON | ON | ON | 0xCE000 | 0xCFFFF | |
| 9 | ON | ON | ON | ON | ON | 0xD0000 | 0xD1FFF | |
| 10 | ON | ON | ON | ON | ON | 0xD2000 | 0xD3FFF | |
| 11 | ON | ON | ON | ON | ON | 0xD4000 | 0xD5FFF | |
| 12 | ON | ON | ON | ON | ON | 0xD6000 | 0xD7FFF | |
| 13 | ON | ON | ON | ON | ON | 0xD8000 | 0xD9FFF | |
| 14 | ON | ON | ON | ON | ON | 0xDA000 | 0xDBFFF | |
| 15 | ON | ON | ON | ON | ON | 0xDC000 | 0xDDFFF | |
| 16 | ON | ON | ON | ON | ON | 0xDE000 | 0xDFFFF | |
| 17 | ON | ON | ON | ON | ON | 0xE0000 | 0xE1FFF | |
| 18 | ON | ON | ON | ON | ON | 0xE2000 | 0xE3FFF | |
| 19 | ON | ON | ON | ON | ON | 0xE4000 | 0xE5FFF | |
| 20 | ON | ON | ON | ON | ON | 0xE6000 | 0xE7FFF | |
| 21 | ON | ON | ON | ON | ON | 0xE8000 | 0xE9FFF | |
| 22 | ON | ON | ON | ON | ON | 0xEA000 | 0xEBFFF | |
| 23 | ON | ON | ON | ON | ON | 0xEC000 | 0xEDFFF | |
| 24 | ON | ON | ON | ON | ON | 0xEE000 | 0xEFFFF | |
| 25 | ON | ON | ON | ON | ON | 0xF0000 | 0xF1FFF | |
| 26 | ON | ON | ON | ON | ON | 0xF2000 | 0xF3FFF | |
| 27 | ON | ON | ON | ON | ON | 0xF4000 | 0xF5FFF | |
| 28 | ON | ON | ON | ON | ON | 0xF6000 | 0xF7FFF | |
| 29 | ON | ON | ON | ON | ON | 0xF8000 | 0xF9FFF | |
| 30 | ON | ON | ON | ON | ON | 0xFA000 | 0xFBFFF | |
| 31 | ON | ON | ON | ON | ON | 0xFC000 | 0xFDFFF | |
| 32 | ON | ON | ON | ON | ON | 0xFE000 | 0xFFFFF | |
Firmware
The dual IDE interfaces need a firmware written in the signaling controller to operate properly. While this is just a fancy name for a humble PAL device and its associated JEDEC file, let's play professional up until the end of this project.
Firmware File: firmware.jed
Firmware String: 301.10.FW-1.1A
Since not all of my projects are open-source nor free for educational purposes, it is worth mentioning that the EEPLD firmware is closed-source. However, the compiled JEDEC file can still be used in derivative works of my project, or in any other DIY project, as long as it is non-commercial and the schematic diagram and circuit layout are open-source.
In the end, this EEPLD device and its programming was one of the main desire factors that led me to build this I/O interface. As a funny fact, back in 1995 or 1996, while I was literally staring at a UNiSYS 80286-10 mainboard, I really wondered what those AMD badged PAL integrated circuits were anyway. If I remember correctly, they were PAL22V10 in J-type ceramic package. I said to myself that one day I will build something using PAL ICs. Strangely, now my appetite for these devices is increasing.
ROM BIOS
In the future I am planning to write a ROM BIOS program that will perform autodetection of each IDE drive that might be connected to either of the IDE interfaces. This BIOS will take full control over the system ROM BIOS, in terms of IDE settings.
Unfortunately, this functionality is not available at this time. In the meantime, I have set up a GitHub repository where I uploaded initial project files. Things are slowly progressing as I'm struggling to recover my assembly programming skills. For the past 15 years I did only Object Pascal and C++ programming. So I am a little bit rusty, to be nice to myself. To be honest, I'm well off course. I barely remembered how to address the VGA video RAM segment to output some text. Next, I'll see what I can do with the ATA identify command so I can obtain the IDE device parameters. It is going to be fun, for sure.
GitHub Repository: https://github.com/agroza/IOIF-ROM-BIOS
ROM #0 Main Assembly Program: ioifrom0.asm
After you assemble the ROM file, an 8-bit checksum of the dump needs to be calculated and updated within the file. I found a lot of scripts on the Internet to do this but they were either Linux shell scripts or Python. And I have none of those installed on any of my machines. So I decided to program my own variant in my favorite programming language.
GitHub Repository: https://github.com/agroza/romcksum
Main Program: romcksum.dpr
Known Issues
For some reason, the floppy disk drive controller does not work with fast computers. For instance, it triggers seek errors and hardware faults if I try to use it with a Pentium MMX 233 MHz processor. The controller works OK if I turn off the internal CPU cache. I believe the controller can't keep up either with the fast CPU or the DMA controller implemented in this particular chipset.
This is a topic that requires further investigations.
Construction and Pictures (VER. 1.4 REV. C)
The PCBs have arrived from the factory. Thus, let's move on with the assembly. As with all large PCBs, the pictures present a certain amount of barrel distortion. I took them with my Nokia 6.1 mobile phone. Funnily enough, in certain conditions, it takes better pictures than my standalone digital still camera.
This is the bare 4-layer PCB, components side.
And this is the solder side.
Small signal diodes and individual resistors are all in.
I don't really like soldering small components since I can always feel heat discomfort on the tip of my left index finger. Luckily there are only a handful of glass diodes and individual resistors on this PCBa.
Miniature glass beads for the MLCC capacitors and the ferrite beads. And they are translucent-purple!
Purple glamour... Electronics porn... You name it.
All MLCC parts are soldered in.
Radio frequency filtering beads are in position.
Soldering these little parts was tedious and took longer than I expected.
I always liked soldering IC sockets. They offer some kind of instant gratification.
I particularly like the brown PLCC sockets. I spent a fair amount of time searching for brown sockets as most of them were standard black.
All other components are soldered. I also added a card steel bracket that I stole from an old controller card. I polished it first as it was very dirty.
Then I inserted the ICs in their respective sockets. However, I haven't fully pushed the ATF16V8 EEPLD, yet. I programmed it but I will run some tests first. Once the EEPLD firmware is validated then I'll push it in completely. I installed only one ROM IC for the moment. And I designed a small auto-adhesive label for it. MPTEC is the abbreviation for Microprogramming TECHNIQUES. That's the name under which I release all my software products. I think I came with this name when I was 14 or so. At the time I was learning assembly language. I was also very attracted to minimization and optimization techniques. So I thought about a name that summarized what I was doing.
And now: that what-the-fuck moment we all strive to avoid. I bet you didn't observe in the pictures above that the primary IDE interface connector is mounted in reverse. Fatigue and enthusiasm made me rush out and mess things up. Here you go. Desoldering 40 pins on a 4 layer PCB is not fun at all.
But I did it after all. It took me about half an hour of work with the precision solder sucker and the rework station.
Light emitting diodes.
I am missing some parts that were backordered with Mouser. So now I'm waiting for them to arrive. The parts have arrived in the meantime. I soldered all remaining parts in their respective places. Also, switching to the standalone digital still camera for the following pictures.
Details.
It's funny the 93 number on the secondary serial port connector. I don't know what it means but it is exactly the year I touched an AT PC for the first time.
Switches and jumpers.
More switches, more jumpers, and the Holtek parallel port controller.
This is the solder side.
Then I tested the I/O Interface card. First, I disabled the serial, parallel, floppy, and hard disk drive interfaces on the NEAT-575 Pentium ISA Single Board Computer that I am using for testing purposes. And for playing Doom, Duke Nukem 3D, and Quake. Well, Hexen, Heretic, Blood, Network Q RAC Rally, and other forgotten titles as well. The interface works perfectly and I'm getting a constant sustained 2.25 Mb/sec linear data transfer rate with Compact Flash cards. However, the floppy disk drive controller does not work. There is absolutely no reason why it shouldn't work since I closely followed the datasheet suggested schematic. I only replaced the PAL address decoder with some glue logic. But that should not pose any problems. I visualized the address decoding with my scope and everything was alright. What could be wrong then?
I strongly suspect the floppy controller integrated circuit. I think it's fake. I mean I managed to correctly read a 5¼ 1.2 Mb floppy disk. Next, I tried to write some files on it and, despite the fact that the FAT12 structure was updated correctly -- or so it seems -- the files themselves were garbage. Then I tried with another diskette. A 3½ 1.44 Mb floppy this time. I constantly received controller seek error and bad controller errors. I even tried using DiskDupe program, which I used a lot in the 1990s. It failed to initialize the floppy controller. Also, BIOS fails to do floppy drive seek routine. It worked for a couple of minutes, then it went off for good. I bought another chip from eBay in the meantime. This time from a reputable seller. Oh I forgot to say that the first one I bought from China for $ 2.5 or so, free shipping. I mean, really? What was I thinking? There is also the possibility that my chip was ESD-damaged. Or I damaged it somehow.
Here is the dead chip and the new chip. The defective IC has a different marking font. It might have been re-badged at some point. I don't know. Good thing the new chip works.
LEDs.
And lit.
Later Edit: I also made my own IDC data cables for use with this interface.
Constructing a Second I/O Interface
In 2021 I have built another I/O Interface for my second DIY computer. The construction pretty much went flawlessly and it took me less time to assemble everything than the first time. I haven't respected the order of placing the parts on the PCB but I was so enthusiastic that I soldered every part that I had at hand, without planning ahead soldering small components first and larger ones next.
This time I filed out all the factory alignment dents before actually planting any component on the PCB.
Small components soldered on the PCB.
Random parts are soldered next.
IC sockets are now in position.
The finalized PCB assembly. At this time I haven't inserted any IC.
Detail on the EPROM configuration switches.
Again, shiny LEDs.
Detail on IDE interface connectors.
Detail on the parallel and serial I/O interfaces.
IC sockets. For all my prototypes I like to uses sockets. In case of errors or if I want to experiment with different ICs, I can easily operate changes.
All logic ICs are now inserted in their respective sockets.
And finally, the solder side.
I have inserted a 512 Mb IDE flash module into the primary IDE interface connector. It is configured as the master drive. In addition, it will be drawing power directly from the I/O Interface itself through pin 20 of the IDE interface connector. For this purpose I will install jumper in position JP5.
There is one drawback though. This particular Transcend IDE flash module does not trigger the /IDE-ACT signal. This means there will be no activity LEDs lit when the flash module is reading or writing data.
And because I just can't get enough of computer-world industrial design and LEDs, next comes another macro picture.
That's it for now.
Versions and Revisions
This section lists the project version and revision history.
VER. 1.4 REV. D
- Fully functional production version
- Added jumper to enable or disable the floppy disk drive interface
- Added jumpers to enable or disable the IDE interfaces data lines pull-up resistors
- Added jumpers to bind IDE interfaces pin 28 (SPSYNC:CSEL signal) either as GND or ALE signals
- Fixed some wrong PCB tracks angles
- Various PCB tracks improvements
- Card edge connector gold fingers are now longer
- Resistor array RA3 was incorrectly referenced as RN9
- Renamed some of the configuration jumpers
- Various silkscreen updates
VER. 1.4 REV. C
- Fully functional initial prototype version
Copyright © 2004- Alexandru Groza
All rights reserved.
VER. 1.0 | REV. A